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SNVS441F – JANUARY 2007 – REVISED FEBRUAY 2013
IO Levels
I 2 C interface, CLK_32K and TRIG pins input levels are defined by EN pin. Using EN pin as voltage reference for
logic inputs simplifies PWB routing and eliminates the need for dedicated V IO pin. In the following block diagram
is described EN pin connections.
VDD
Input
EN
SDA
SCL
Buffer
Level
Shifter
Level
Shifter
Figure 27. Using EN pin as digital IO voltage reference
ADDR_SEL0/1 are referenced to V DD voltage. GPO pin level is defined by V DD voltage.
GPO/INT pins
LP5521 has one General Purpose Output pin (GPO) and also INT pin can be configured as a GPO pin. When
INT is configured as GPO output, it's level is defined by the V DD voltage. State of the pins can be controlled with
GPO register (0EH). GPO pins are digital CMOS outputs and no pull-up/down resistors are needed.
When INT pin GPO function is disabled, it operates as an open drain pin. INT signal is active low, i.e. when
interrupt signal is sent, the pin is pulled to GND. External pull-up resistor is needed for proper functionality.
Table 18. GPO register (0EH)
Name
INT_AS_GPO
GPO
INT
Bit
2
1
0
Description
Enable INT pin GPO function
0 = INT pin functions as a INT pin
1 = INT pin functions as a GPO pin
0 = GPO pin state is low
1 = GPO pin state is high
0 = INT pin state is low (INT_AS_GPO=1)
1 = INT pin state is high (INT_AS_GPO=1)
TRIG pin
TRIG pin can function as an external trigger input or output. External trigger signal is active low, i.e. when trigger
is sent/received the pin is pulled to GND. TRIG is an open drain pin and external pull-up resistor is needed for
trigger line. External trigger input signal must be at least two 32 kHz clock cycles long to be recognized. Trigger
output signal is three 32 kHz clock cycles long. If TRIG pin is not used on application, it should be connected to
GND to prevent floating of this pin and extra current consumption.
ADDR_SEL0,1 pins
ADDR_SEL0,1 pins define the chip I 2 C address. Pins are referenced to V DD signal level. See I 2 C Compatible
Serial Bus Interface chapter for I 2 C address definitions.
CLK_32K pin
CLK_32K pin is used for connecting external 32 kHz clock to LP5521. External clock can be used to synchronize
the sequence engines of several LP5521. Using external clock can also improve automatic power save mode
efficiency, because internal clock can be switched off automatically when device has entered power save mode,
and external clock is present. See application note “LP5521 Power Efficiency Considerations” for more
information.
Device can be used without the external clock. If external clock is not used on the application, CLK_32K pin
should be connected to GND to prevent floating of this pin and extra current consumption.
22
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